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fujitsu semiconductor data sheet 8-bit proprietary microcontroller cmos f 2 mc-8l mb89560h series MB89567h/567hc/p568/pv560 n description the mb89560h series has been developed as a general-purpose version of the f 2 mc*-8l family consisting of proprietary 8-bit, single-chip microcontrollers. in addition to a compact instruction set, the microcontroller contains a variety of peripheral functions such as i 2 c interface, timers, 2 ch pwm timers, 8/16-bit timer, 21bit timebase timer, 8 bit pwc timer , 17-bit watch prescaler, watch-dog timer, high speed uart, 8-bit sio, uart/sio, lcd controller/driver (optional booster), two type programmable pulse generators (ppg), an a/d converter, and external interrupt. *: f 2 mc stands for fujitsu flexible microcontroller. n features ?f 2 mc-8l family cpu core ? low-voltage operation (when an a/d converter is not used) ? low current consumption (applicable to the dual-clock system) ? minimum execution time: 0.32 m s at 12.5 mhz ?i 2 c interface circuit ? lcd controller/driver : 24 segments x 4 commons (max. 96 pixels, duty lcd mode and static lcd mode) ? lcd booster function (option) ? wild register (max. 6 different address locations) ? 10-bit a/d converter: 8 channels (continued) n package 80-pin plastic lqfp 80-pin ceramic mqfp 80-pin plastic qfp 80-pin plastic lqfp (mqp-80c-p01) (fpt-80p-m11) (fpt-80p-m06) (fpt-80p-m05) fpt-80p-m11 fpt-80p-m06 fpt-80p-m05 mqp-80c-p01
2 mb89560h series (continued) ? three types of serial interface: high speed uart ( transfer rate from 300 to 192000 bps /10 mhz main clock) 8-bit serial i/o (sio) uart/sio ? two type of programmable pulse generator(ppg) : 6-bit ppg and 12-bit ppg ? six types of timer 8 bit pwm 2 channels timers 8/16 bit timer/counter (8 bits x 2 channels or 16 bits x 1 channel) 21bit timebase timer 8 bit pwc timer operation watch prescaler(17 bits) watch-dog timer ? i/o ports: max. 50 channels ? external interrupt 1: 8 channels ? external interrupt 2 (wake-up function): 4 channels ? low-power consumption modes (stop mode, sleep mode, and watch mode) ? lqfp-80 and qfp-80 package ? cmos technology n product lineup MB89567h MB89567hc mb89p568 mb89pv560 classification mass production products (mask rom products) otp piggy-back rom size 32 k 8 bits (internal mask rom) 48 k 8 bits (internal prom) 56 k 8 bits (external rom) ram size 1k 8 bits 1k 8 bits cpu functions number of instructions: : 136 instruction bit length: : 8 bits instruction length: : 1 to 3 bytes data bit length: : 1, 8, 16 bits minimum execution time: : 0.4 m s/10 mhz minimum interrupt processing time: : 3.6 m s/10 mhz ports general-purpose i/o ports (n-channel open drain) : 20 pins (2 shared with i 2 c inputs, 16 shared with lcd, 2 shared with other resources) general-purpose i/o ports (cmos) : 30 pins (shared with resources) total : 50 pins 21-bit timebase timer 21 bits interrupt cycle: 2 11 , 2 13 , 2 16 or 2 20 t inst * 5 watchdog timer reset generate cycle: min. 2 20 t inst for main clock, min. 2 13 t inst for sub clock watch prescaler 17 bits interrupt cycle: 0.50s, 1.00s, 2.00s, 4.00s/32.768 khz for subclock 8/16-bit timer/ counter can be operated either as a 2-channel 8-bit timer/counter (timer 1 and timer 2, each with its own independent operating clock cycle), or as one 16-bit timer/counter in timer 1 or 16-bit timer/counter operation, event counter operation (external clock-triggered) and square wave output capable 8-bit pwm 2 ch timer 8-bit interval timer operation (square wave output capable, operating clock cycle: 1, 8, 16, 64 t inst ) 8-bit resolution pwm operation (conversion cycle: 256 to 256 x 64 t inst ) 8/16-bit timer/counter output for counter clock selectability part number parameter
3 mb89560h series * :varies with conditions such as the operating frequency. ( see n electrical characteristics.) *1 : when booster is used, the bias is reduced by 1/3. it can be selected by mask option. *2 : when the a/d converter is used, operating voltage must be 3.5v to 5.5v. *3 : use mbm27c512-20 as the external rom (operating voltage: 4.5 v to 5.5 v) *4 : i 2 c is complied to intel corp. system management bus rev. 1.0 specification and to the philips i 2 c specification. *5 : 1 tinst = one instruction cycle (execution time) which can be selected as 1/4, 1/8, 1/16, or 1/64 of main clock if main clock mode is selected , or 1/2 of the subclock if subclock mode is selected pwc timer 8-bit timer operation (count clock cycle: 1, 4, 32 t inst ) 8-bit reload timer operation (toggle output possible, operating clock cycle: 1 - 32 t inst ) 8-bit pulse width measurement (continuous measurement possible: high and low widths, h to h, l to l, period & h at same time and high & rising to rising) 10-bit a/d con- verter* 2 10-bit resolution 8 channels a/d conversion function (conversion time: 60 t inst ) continuous activation by an 8/16-bit timer/counter output or a timebase timer output capable. 6 bit ppg internal 6-bit counter pulse width and cycle are program selectable 12 bit ppg internal 12-bit counter pulse width and cycle are program selectable i 2 c interface* 4 not available 1 channel use a 2-wire protocol to communicate with other device high speed uart transfer data length: 4, 6, 7, 8 bits transfer rate (300 to 192000 bps /10 mhz main clock) support sub-clock mode uart/sio transfer data length: 7, 8 bits for uart, 8 bits for sio transfer rate (1201 to 78125 bps / 10 mhz main clock) support sub-clock mode 8-bit serial i/o 8 bits, lsb first/msb first selectability one clock selectable from four transfer clocks (one external shift clock, three internal shift clocks: 2, 8, 32 t inst ) lcd common output: 4 (max.) segment output: 24 (max.) lcd driving power (bias) pins: 4 lcd display ram size: 12 bytes (24 4 bits, max. 96 pixels) duty lcd mode and static lcd mode booster for lcd driving: option dividing resister for lcd driving: built-in* 1 wild register maximum of 6-byte data can be assigned in 6 different address. used to replace any data in the rom when specific address and data are assigned in wild register. wild register can be set up by using different communication methods through the device. external interrupt 1 (wake-up function) 8 independent channels (interrupt vector, request flag, request output enable) edge selectability (rising/falling) used also for wake-up from stop/sleep mode. (edge detection is also permitted in stop mode.) external interrupt 2 (wake-up function) 4 channels (l level interrupts, independent input enable). used also for wake-up from stop/sleep mode. (low-level detection is also permitted in stop mode.) standby mode sleep mode, stop mode and clock mode process cmos operating voltage* 3.5 v to 5.5 v 3.5 v to 5.5 v 2.7 to 5.5 v 2.7 to 5.5 v* 3 MB89567h MB89567hc mb89p568 mb89pv560 part number parameter
4 mb89560h series n package and corresponding products n differences among products 1. memory size before evaluating using the otprom (one-time prom) products, verify its differences from the product that will actually be used. take particular care on the following points: ? the stack area, etc., is set at the upper limit of the ram. 2. current consumption ? for the mb89pv560, add the current consumed by the eprom mounted in the piggy-back socket. ? when operating at low speed, the current consumed by the one-time prom product is greater than for the mask rom product. however, the current consumption is roughly the same in sleep or stop mode. ? (for more information, see n electrical characteristics.) 3. mask options the functions available as options and the method of specifying options differ between products. before using options check n mask options. 4. functionalities different between products in mb89560h series note: for more information on t inst see n electrical characteristics (4) instruction cycles" * : instruction cycle package MB89567h MB89567hc mb89p568-101 mb89p568-102 mb89pv560-101 mb89pv560-102 fpt-80p-m05 fpt-80p-m06 fpt-80p-m11 mqp-80c-p01 functionalities MB89567h MB89567hc mb89p568 mb89pv560 power-on reset wait time regulator stab. time + regulator recovery. time + osc. stab. time regulator stab. time + osc. stab. time osc. stab. time wait time for external reset in stop/sub/clock mode or wait time for external interrupt trigger recover from main stop mode regulator recovery time + osc. stab. time osc. stab. time port pin pullup resistors selectable by software. not available. ad conversion time 60 t inst *33 t inst * i 2 c noise cancelling circuit always available independent of iccr:dmbp bit selection. not available when iccr:dmbp bit is asserted.
5 mb89560h series n pin assignment seg07 p50/seg08 p51/seg09 p52/seg10 p53/seg11 p54/seg12 p55/seg13 p56/seg14 p57/seg15 p60/seg16 p61/seg17 p62/seg18 vss p63/seg19 p64/seg20 p65/seg21 p64/seg22 p67/seg23 avr avcc (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 p44/uck/sck1 p43/pwm2/ppg2 p42/pwm1/ec1 p41/hck/to12 p40/wto/to11 p31/sda p30/scl vcc p27/int23 p26/int22 p25/int21 p24/int20 p23/ppg1 p22/sck p21/so p20/si x1 x0 moda x1a seg06 seg05 seg04 seg03 seg02 seg01 seg00 com3 com2 com1 com0 v3 v2 v1 v0 c0 c1 p47/pwc p46/ui/si1 p45/uo/so1 p07/an7 p06/an6 p05/an5 p04/an4 p03/an3 p02/an2 p01/an1 p00/an0 avss p17/int17 p16/int16 p15/int15 p14/int14 p13/int13 p12/int12 p11/int11 c p10/int10 rst x0a (fpt-80p-m05) (fpt-80p-m11)
6 mb89560h series seg05 seg06 seg07 p50/seg08 p51/seg09 p52/seg10 p53/seg11 p54/seg12 p55/seg13 p56/seg14 p57/seg15 p60/seg16 p61/seg17 p62/seg18 vss p63/seg19 p64/seg20 p65/seg21 p66/seg22 p67/seg23 avr avcc p07/an7 p06/an6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 p46/ui/si1 p45/uo/so1 p44/uck/sck1 p43/pwm/ppg2 p42/pwm1/ec1 p41/hck/to12 p40/wto/to11 p31/sda p30/scl vcc p27/int23 p26/int22 p25/int21 p24/int20 p23/ppg1 p22/sck p21/so p20/si x1 x0 moda x1a x0a rst seg04 seg03 seg02 seg01 seg00 com3 com2 com1 com0 v3 v2 v1 v0 c0 c1 p47/pwc p05/an5 p04/an4 p03/an3 p02/an2 p01/an1 p00/an0 avss p17/int17 p16/int16 p15/int15 p14/int14 p13/int13 p12/int12 p11/int11 c p10/int10 (top view) fpt-80p-m06
7 mb89560h series (mqp-80c-p01) seg05 seg06 seg07 p50/seg08 p51/seg09 p52/seg10 p53/seg11 p54/seg12 p55/seg13 p56/seg14 p57/seg15 p60/seg16 p61/seg17 p62/seg18 vss p63/seg19 p64/seg20 p65/seg21 p66/seg22 p67/seg23 avr avcc p07/an7 p06/an6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 p46/ui/si1 p45/uo/so1 p44/uck/sck1 p43/pwm/ppg2 p42/pwm1/ec1 p41/hck/to12 p40/wto/to11 p31/sda p30/scl vcc p27/int23 p26/int22 p25/int21 p24/int20 p23/ppg1 p22/sck p21/so p20/si x1 x0 moda x1a x0a rst seg04 seg03 seg02 seg01 seg00 com3 com2 com1 com0 v3 v2 v1 v0 c0 c1 p47/pwc p05/an5 p04/an4 p03/an3 p02/an2 p01/an1 p00/an0 avss p17/int17 p16/int16 p15/int15 p14/int14 p13/int13 p12/int12 p11/int11 c p10/int10 101 102 103 104 105 106 107 108 109 93 92 91 90 89 88 87 86 85 110 111 112 81 82 83 84 100 99 98 97 96 95 94 *1 :pin assignment on package top (mb89pv560 only) n.c.: internally connected. do not use. pin no. pin name pin no. pin name pin no. pin name pin no. pin name 81 n.c. 89 ad2 97 n.c. 105 oe 82 a15 90 ad1 98 04 106 n.c. 83 a12 91 ad0 99 o5 107 a11 84 ad7 92 n.c. 100 o6 108 a9 85 ad6 93 o1 101 07 109 a8 86 ad5 94 o2 102 o8 110 a13 87 ad4 95 o3 103 ce 111 a14 88 ad3 96 vss 104 a10 112 vcc *1 (top view)
8 mb89560h series n pin description (continued) *1: fpt-80p-m05 *2: fpt-80p-m11 *3: mqp-80c-p01 *4: fpt-80p-m06 pin no. pin name i/o circuit type function lqfp* 1 lqfp* 2 mqfp* 3 qfp* 4 43 45 x0 a crystal or other resonator connector pins for the main clock. the external clock can be connected to x0. when this is done, be sure to leave x1 open. cr oscillation selectability in model with a mask rom only. 44 46 x1 42 44 moda c memory access mode setting pins. connect directly to vss. hysteresis input type. 39 41 rst d reset i/o pin this pin is a cmos output type with a pull-up resistor, and a hysteresis input type. l is output from this pin by an internal reset request (optional). the internal circuit is initialized by the input of l. 49 to 52 51 to 54 p24/int20 to p27/int23 e general-purpose cmos i/o ports also serve as an external interrupt 2 input (wake-up function). external interrupt 2 input is hysteresis input. selectable pull-up resistor. 30 to 36 ,38 32 to 38,40 p10/int10 to p17/int17 e general-purpose cmos i/o ports also serve as input for external interrupt 1 input. external interrupt 1 input is hysteresis input. selectable pull-up resistor. 60 62 p44/uck/ sck1 e general-purpose cmos i/o ports also serve as the clock i/o for the high-speed uart and serial io. the peripheral is a hysteresis input type. selectable pull-up resistor. 61 63 p45/uo/so1 f general-purpose cmos i/o ports also serves as the data output for the high-speed uart and serial i/o. the peripheral is a hysteresis input type. selectable pull-up resistor. 62 64 p46/ui/si1 g n-ch open drain general-purpose i/o ports also serves as the data input for the high-speed uart and serial i/o. the peripheral is a hysteresis input type. 63 65 p47/pwc g n-ch open drain general-purpose i/o port also serve as the external clock input for pwc. the peripheral is a hysteresis input. 56 58 p40/wto/ to11 f general-purpose cmos i/o port also serves as an 8/16-bit timer/counter output and pwc output.
9 mb89560h series (continued) (continued) *1: fpt-80p-m05 *2: fpt-80p-m11 *3: mqp-80c-p01 *4: fpt-80p-m06 pin no. pin name i/o circuit type function lqfp* 1 lqfp* 2 mqfp* 3 qfp* 4 57 59 p41/hck/ to12 f general-purpose cmos i/o port also serves as an 8/16-bit timer/counter output. and half of main clock output selectable pull-up resistor. 45 47 p20/si e general-purpose cmos i/o port also serves as the data input for the serial i/o. the peripheral is a hysteresis input type. selectable pull-up resistor. 46 48 p21/so f general-purpose cmos i/o port also serves as the data output for the serial i/o. selectable pull-up resistor. 47 49 p22/sck e general-purpose cmos i/o port also serves as the clock i/o for the serial i/o. the peripheral is a hysteresis input type. selectable pull-up resistor. 48 50 p23/ppg1 f general-purpose cmos i/o port also serves as the 6 bit programmable pulse generator. selectable pull-up resistor. 54 56 p30/scl g n-ch open-drain general-purpose i/o port data i/o pin for i 2 c interface 55 57 p31/sda g n-ch open-drain general-purpose i/o port data i/o pin for i 2 c interface 65 67 c0 function as capacitor connection pin in the products with a booster. 64 66 c1 function as capacitor connection pin in the products with a booster. 59 61 p43/pwm2/ ppg2 f general-purpose cmos i/o port also serves pwm wave output for the 8-bit pwm timer 1 and as 12 bit programmable pulse generator output. selectable pull-up resistor. 58 60 p42/pwm1/ ec1 e general-purpose cmos i/o port also serves as the pwm wave output and external clock for the 8/16 bit timer counter. selectable pull-up resistor. 21 to 28 23 to 30 p00/an0 to p07/an7 j general-purpose cmos i/o ports also serve as the analog input for the a/d converter. selectable pull-up resistor. 10 to 12 14 to 18 12 to 14 16 to 20 p60/seg16 to p67/seg23 h/i n-ch open-drain general-purpose output ports also serve as an lcd controller/driver segment output. 2 to 9 4 to 11 p50/seg8 to p57/seg15 h/i n-ch open-drain general-purpose output ports also serve as an lcd controller/driver segment output.
10 mb89560h series (continued) *1: fpt-80p-m05 *2: fpt-80p-m11 *3: mqp-80c-p01 *4: fpt-80p-m06 *5: when mb89pv560-101 or mb89pv560-102 is used, this pin will become a nc pin without internal connection. when mb89p568-101 or mb89p568-102 is used, this pin will be select a regulator stabilization delay time. if 5v used in mb89p568-101 or mb89p568-102, this pin must be connected to vss. if 3v used in mb89p568-101 or mb89p568-102, this pin must be connected to vcc. if MB89567h or MB89567hc is used, 0.1 m f capacitor should connect to this pin. pin no. pin name i/o circuit type function lqfp* 1 lqfp* 2 mqfp* 3 qfp* 4 74 to 80, 1 1 to 3 76 to 80 seg0 to seg7 i lcd controller/driver segment output-only pins 70 to 73 72 to 75 com0 to com3 i lcd controller/driver common output-only pins 68 to 71 70 to 73 v0 to v3 lcd driving power supply pins. 42 44 x0a b crystal or other resonator connector pins for the subclock (subclock: 32.768 khz) the external clock can be connected to x0a. when this is done, be sure to leave x1a open. 43 45 x1a 55 57 vcc power supply pin 39 41 c capacitor connection pin *5 15 17 vss power supply (gnd) pin 22 24 avcc a/d converter power supply pin 21 23 avr a/d converter reference voltage input pin 31 33 avss a/d converter power supply pin use this pin at the same voltage as vss.
11 mb89560h series n pin description for external eprom socket (mb89pv560 only) pin no. pin name i/o function 82 83 84 85 86 87 88 89 90 91 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 o address output pins 93 94 95 o1 o2 o3 i data input pins 96 vss o power supply (gnd) pin 98 99 100 101 102 o4 o5 o6 o7 o8 i data input pins 103 ce o rom chip enable pin outputs h during standby. 104 a10 o address output pin 105 oe/ v pp o rom output enable pin outputs l at all times. 107 108 109 a11 a9 a8 o address output pins 110 a13 o 111 a14 o 112 vcc o eprom power supply pin 81 92 97 106 n.c. internally connected pins be sure to leave them open.
12 mb89560h series n i/o circuit type (continued) type circuit remarks a main clock (main clock crystal oscillator) ? at an oscillation feedback resistor of approximately 1 m w /5.0 v ? cr oscillation is selectable (mask products only) b subclock (subclock crystal oscillator) ? at an oscillation feedback resistor of approximately 4.5 m w /5.0 v c ? hysteresis input d ?cmos output ? hysteresis input ? at an output pull-up resistor (p-ch) of approximately 50 k w /5.0 v e ? cmos output ? cmos input ? the peripheral is a hysteresis input type. ? selectable pull-up resistor (p-ch) of approximately 50 k w /5.0 v x1 x0 n-ch p-ch p-ch n-ch n-ch x1a x0a n-ch p-ch p-ch n-ch n-ch p-ch n-ch r p-ch n-ch r p-ch port pull up resistor register peripheral
13 mb89560h series (continued) type circuit remarks f ? cmos output ? cmos input ? selectable pull-up resistor (p-ch) of approximately 50 k w /5.0 v g ? n-ch open-drain input/output ? cmos input ? the peripheral is a hysteresis input type. h ? n-ch open-drain output ? cmos input i ? lcd controller/driver common/segment output j ? general cmos i/o ? analog input (a/d converter) ? selectable pull-up resistor (p-ch) of approximately 50 k w /5.0 v ? pull-up resistors must be disabled when used as an analog input). p-ch n-ch r p-ch pull up resistor register port n-ch peripheral port n-ch port n-ch p-ch p-ch n-ch n-ch r p-ch p-ch analog input pull up resistor register port aden
14 mb89560h series n handling devices 1. preventing latchup latchup may occur on cmos ics if voltage higher than v cc or lower than v ss is applied to input and output pins other than medium- to high-voltage pins or if higher than the voltage which shows on 1. absolute maximum ratings in n electrical characteristics is applied between v cc and v ss . when latchup occurs, power supply current increases rapidly and might thermally damage elements. when using, take great care not to exceed the absolute maximum ratings. also, take care to prevent the analog power supply (av cc and avr) and analog input from exceeding the digital power supply (v cc ) when the analog system power supply is turned on and off. 2. treatment of unused input pins leaving unused input pins open could cause malfunctions. they should be connected to a pull-up or pull-down resistor. 3. treatment of power supply pins on microcontrollers with a/d and d/a converters connect to be av cc = davc = v cc and av ss = avr = v ss even if the a/d and d/a converters are not in use. 4. treatment of n.c. pins be sure to leave (internally connected) n.c. pins open. 5. power supply voltage fluctuations although v cc power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. stabilizing voltage supplied to the ic is therefore important. as stabilization guidelines, it is recommended to control power so that v cc ripple fluctuations (p-p value) will be less than 10% of the standard v cc value at the commercial frequency (50 to 60 hz) and the transient fluctuation rate will be less than 0.1 v/ms at the time of a momentary fluctuation such as when power is switched. 6. precautions when using an external clock even when an external clock is used, oscillation stabilization time is required for power-on reset and wake-up from stop mode.
15 mb89560h series n programming to the eprom on the mb89p568 the mb89p568 is an otprom version of the MB89567h and MB89567hc. 1. features ? 48-kbyte prom on chip ? equivalency to the mbm271001a in eprom mode (when programmed with the eprom programmer) 2. memory space memory space in eprom mode is diagrammed below. 3. programming to the eprom in eprom mode, the mb89p568 functions equivalent to the mbm27c1001a. this allows the prom to be programmed with a general-purpose eprom programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. ? programming procedure (1) set the eprom programmer to the mbm27c1001a. (2) load program data into the eprom programmer at 4000 h to ffff h (3) program with the eprom programmer. i/o ram not available program area (prom) program area (prom) 4000 h ffff h 0000 h 0080 h 0480 h ffff h 4000 h normal operation eprom mode (corresponding addresses on the eprom programmer
16 mb89560h series 4. recommended screening conditions high-temperature aging is recommended as the pre-assembly screening procedure. 5. programming yield all bits cannot be programmed at fujitsu shipping test to a blanked otprom microcomputer, due to its nature. for this reason, a programming yield of 100% cannot be assured at all times. 6. eprom programmer socket adapter inquiry: sun hayato co., ltd.: tel 81-3-3802-5760 package compatible socket adapter fpt-80p-m05 rom-80sqf-32dp-8la fpt-80p-m06 rom-80qf-32dp-8la2 fpt-80p-m11 rom-80sqf-32dp-8la program, verify aging +150?, 48 hrs. data verification assembly
17 mb89560h series n programming to the eprom with piggyback/evaluation device 1. eprom for use mbm27c512-20tv 2. programming socket adaptor to program to the prom using an eprom programmer, use the socket adaptor (manufacturer: sun hayato co., ltd.) listed below. inquiry: sun hayato co., ltd.: tel 81-3-5396-9106 3. memory space 4. programming to eprom (1) set the eprom programmer to the mbm27c512. (2) load program data into the eprom programmer at 2000 h to ffff h . (3) program to 2000 h to ffff h with the eprom programmer. package adaptor socket part number lcc-32 (rectangle) rom-32lc-28dp-yg i/o ram not available program area (prom) program area (prom) 0000 h 0080 h 2000 h ffff h ffff h 2000 h normal operation (corresponding addresses on the eprom programmer) 0480 h
18 mb89560h series n block diagram oscillator clock controller low-power oscillator (32.768 khz) 1k byte ram f 2 mc-8l cpu 48k byte rom other pins moda, c, v cc , v ss internal data bus 21-bit time-base uart/sio port 2 cmos i/o port port 5 & port 6 *1: output of main clock/2. *2 : i 2 c is not available in MB89567 and MB89567h. *3 : selected by mask option *4 : can be used as a 16-bit timer/counter by connecting timer 1 output to timer 2 input. x0 x1 p10/int10 to p17/int17 p23/ppg1 p20/si p21/so p22/sck timer main clock watch prescaler reset circuit (watchdog timer) rst x0a x1a port 1 cmos i/o port external interrupt 2 (wake-up function) port 4 8 8 p24/int20 to p27/int23 4 4 port 0 cmos i/o port 10-bit a/d converter p00/an0 to p07/an7 8 8 av cc av ss n-ch open-drain i/o port lcd controller/ driver display ram (12 bytes) 8-bit pwm timer 1 p60/seg16 to p63/seg19 p64/seg20 to p67/seg23 p50/seg8 to p53/seg11 p54/seg12 to p57/seg15 seg0 to seg7 8 com0 to com3 4 v0 to v3 4 8 8 subclock 8-bit pwm timer 2 avr port 3 n-ch open drain i/o port i 2 c *2 p30/scl p31/sda c0* 3 c1* 3 8-bit timer/counter 1 (timer 1) *4 8-bit timer/counter 2 (timer 2) *4 pwc sio p40/wto/to11 p41/hck *1 /to12 p42/pwm1/ec1 p43/pwm2/ppg2 p44/uck/sck1 p45/uo/so1 p46/ui/si1 p47/pwc wild register high-speed external interrupt 1 booster option 12 bit ppg 6 bit ppg uart cmos i/o port (p46 and p47 are n-ch open-diran i/o type) 4 4 4 4
19 mb89560h series n cpu core 1. memory space the microcontrollers of the mb89560h series offer a memory space of 64 kbytes for storing all of i/o, data, and program areas. the i/o area is located the lowest address. the data area is provided immediately above the i/ o area. the data area can be divided into register, stack, and direct areas according to the application. the program area is located at exactly the opposite end, that is, near the highest address. provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. the memory space of the mb89560h series is structured as illustrated below. memory space i/o ram rom mb89p568-101,102 0000 h 0080 h 0100 h 0200 h 0480 h ffc0 h ffff h 4000 h access prohibited registers i/o ram rom MB89567h, MB89567hc 0000 h 0080 h 0100 h 0200 h ffc0 h ffff h 8000 h registers external *1 *1: mb89p568-101,102 has otp rom inside *2 : wild register setting registers i/o ram rom mb89pv560-101,102 0000 h 0080 h 0100 h 0200 h 0480 h ffc0 h ffff h 2000 h access prohibited registers external *1 0492 h 0492 h *2 *2 0492 h *2 0480 h access prohibited
20 mb89560h series 2. registers the f 2 mc-8l family has two types of registers; dedicated registers in the cpu and general-purpose registers in the memory. the following registers are provided: program counter (pc): a 16-bit register for indicating specifies instruction storage positions. accumulator (a): a 16-bit temporary register for storing arithmetic operations, etc. when the instruction is an 8-bit data processing instruction, the lower byte is used. temporary accumulator (t): a 16-bit register which performs arithmetic operations with the accumulator when the instruction is an 8-bit data processing instruction, the lower byte is used. index register (ix): a 16-bit register for index modification extra pointer (ep): a 16-bit pointer for indicating a memory address stack pointer (sp): a 16-bit register for indicating a stack area program status (ps): a 16-bit register for storing a register pointer, a condition code the ps can further be divided into higher 8 bits for use as a register bank pointer (rp) and the lower 8 bits for use as a condition code register (ccr). (see the diagram below.) pc a t ix ep sp ps 16 bits : program counter : accumulator : temporary accumulator : index register : extra pointer : stack pointer : program status fffd h undefined undefined undefined undefined undefined i-flag = 0, il1, 0 = 11 other bits are undefined. initial value vacancy h i il1, 0 n z vc 54 rp ps 109876 3210 15 14 13 12 11 rp ccr vacancy vacancy
21 mb89560h series the rp indicates the address of the register bank currently in use. the relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. the ccr consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of cpu operations at the time of an interrupt. h-flag: set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. cleared otherwise. this flag is for decimal adjustment instructions. i-flag: interrupt is allowed when this flag is set to 1. interrupt is prohibited when the flag is set to 0. set to 0 when reset. il1, 0: indicates the level of the interrupt currently allowed. processes an interrupt only if its request level is higher than the value indicated by this bit. n-flag: set if the msb is set to 1 as the result of an arithmetic operation. cleared when the bit is set to 0. z-flag: set when an arithmetic operation results in 0. cleared otherwise. v-flag: set if the complement on 2 overflows as a result of an arithmetic operation. reset if the overflow does not occur. c-flag: set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. cleared otherwise. set to the shift-out value in the case of a shift instruction. il1 il0 interrupt level high-low 00 1 high low = no interrupt 01 10 2 11 3 rule for conversion of actual addresses of the general-purpose register area ? a15 ? a14 ? a13 ? a12 ? a11 ? a10 ? a9 ? a8 r4 a7 r3 a6 r2 a5 r1 a4 r0 a3 b2 a2 b1 a1 b0 a0 lower op codes rp generated addresses
22 mb89560h series the following general-purpose registers are provided: general-purpose registers: an 8-bit resister for storing data the general-purpose registers are 8 bits and located in the register banks of the memory. one bank contains eight registers. up to a total of 32 banks can be used on MB89567h and MB89567hc. the bank currently in use is indicated by the register bank pointer (rp). register bank configuration this address = 0100 h + 8 (rp) memory area 32 banks (MB89567h/567hc) r 0 r 1 r 2 r 3 r 4 r 5 r 6 r 7
23 mb89560h series n i/o map (continued) address register name register description read/write initial value 00 h pdr0 port 0 data register r/w xxxxxxxx b 01 h ddr0 port 0 data direction register w 00000000 b 02 h pdr1 port 1 data register r/w xxxxxxxx b 03 h ddr1 port 1 data direction register w 00000000 b 04 h - 06 h (vacancy) 07 h sycc system clock control register r/w xxxmm100 b 08 h stbc standby control register r/w 00010xxx b 09 h wdtc watchdog timer control register w 0xxxxxxx b 0a h tbtc timebase timer control register r/w 00xxx000 b 0b h wpcr watch prescaler control register r/w 00xx0000 b 0c h pdr2 port 2 data register r/w xxxxxxxx b 0d h ddr2 port 2 data direction register r/w 00000000 b 0e h pdr3 port 3 data register r/w xxxxxx11 b 0f h pdr4 port 4 data register r/w xxxxxxxx b 10 h ddr4 port 4 direction register r/w 00000000 b 11 h pdr5 port 5 data register r/w 00000000 b 12 h (vacancy) 13 h pdr6 port 6 data register r/w 00000000 b 14 h - 19 h (vacancy) 1a h t2cr timer2 control register r/w x000xxx0 b 1b h t2dr timer2 data register r/w xxxxxxxx b 1c h t1cr timer1 control register r/w x000xxx0 b 1d h t1dr timer1 data register r/w xxxxxxxx b 1e h - 21 h (vacancy) 22 h smc11 uart1 mode control register 1 r/w 00000000 b 23 h src1 uart1 mode data register r/w xx011000 b 24 h ssd1 uart1 status/data register r/w 00100x1x b 25 h sidr1/sodr1 uart1 data register r/w xxxxxxxx b 26 h smc12 uart1 mode control register 2 r/w xx100001 b 27 h cntr1 pwm control register 1 r/w 00000000 b 28 h cntr2 pwm control register 2 r/w 000x0000 b 29 h cntr3 pwm control register 3 r/w x000xxxx b 2a h comr1 pwm compare register 1 w xxxxxxxx b 2b h comr2 pwm compare register 2 w xxxxxxxx b 2c h pcr1 pwc pulse width control register 1 r/w 000xx000 b 2d h pcr2 pwc pulse width control register 2 r/w 00000000 b 2e h rlbr pwc reload buffer register r/w xxxxxxxx b 2f h smc21 uart2/sio mode control register r/w 00000000 b 30 h smc22 uart2/sio mode control register 2 r/w 00000000 b
24 mb89560h series (continued) (continued) address register name register description read/write initial value 31 h ssd2 uart2/sio status/data register r/w 00001xxx b 32 h sidr2/sodr2 uart2/sio data register r/w xxxxxxxx b 33 h src2 uart2/sio rate control register r/w xxxxxxxx b 34 h adc1 a/d control register 1 r/w x00000x0 b 35 h adc2 a/d control register 2 r/w x0000001 b 36 h addl a/d data register l r/w xxxxxxxx b 37 h addh a/d data register h r/w xxxxxxxx b 38 h rcr21 ppg control register 1(ppg2) r/w 00000000 b 39 h rcr23 ppg control register 2(ppg2) r/w 0x000000 b 3a h rcr22 ppg control register 3(ppg2) r/w xx000000 b 3b h rcr24 ppg control register 4(ppg2) r/w xx000000 b 3c h - 3e h (vacancy) 3f h eic1 external interrupt 1 control register 1 r/w 00000000 b 40 h eic2 external interrupt 1 control register 2 r/w 00000000 b 41 h eic3 external interrupt 1 control register 3 r/w 00000000 b 42 h eic4 external interrupt 1 control register 4 r/w 00000000 b 43 h - 50 h (vacancy) 51 h ibsr i 2 c bus status register r 00000000 b 52 h ibcr i 2 c bus control register r/w 00000000 b 53 h iccr i 2 c clock control register r/w 000xxxxx b 54 h iadr i 2 c address register r/w xxxxxxxx b 55 h idar i 2 c data register r/w xxxxxxxx b 56 h eie2 external interrupt 2 enable register r/w xxxx0000 b 57 h eif2 external interrupt 2 flag register r/w xxxxxxx0 b 58 h rcr1 ppg control register 1(ppg1) r/w 00000000 b 59 h rcr2 ppg control register 2(ppg1) r/w 0x000000 b 5a h ckr clock output control register r/w 00000000 b 5b h lcr1 lcd controller/driver control register 1 r/w 00010000 b 5c h lcr2 lcd controller/driver control register 1 r/w 00000000 b 5d h lcr3 lcd controller/driver control register 1 r/w xx000000 b 5e h ldr1 lcd data register 1 r/w xxxxxxxx b 5f h (vacancy) 60 h - 6f h vram display ram r/w xxxxxxxx b 70 h smr serial i/o mode register r/w 00000000 b 71 h sdr serial i/o data register r/w xxxxxxxx b 72 h purr0 pull-up resister register 0 r/w 11111111 b 73 h purr1 pull-up resister register 1 r/w 11111111 b 74 h purr2 pull-up resister register 2 r/w 11111111 b 75 h purr4 pull-up resister register 4 r/w xx111111 b 76 h (vacancy)
25 mb89560h series (continued) n extend i/o map l read/write access symbols r/w: readable and writable r: read-only w: write-only l initial value symbols 0: the initial value of this bit is 0. 1: the initial value of this bit is 1. x: the initial value of this bit is undefined. m: the initial value of this bit is determined by mask option. note:do not use vacancies. address register name register description read/write initial value 77 h wren wild register enable register r/w xx000000 b 78 h wror wild register data test register r/w xx000000 b 79 h aden a/d port input enable register r/w 11111111 b 7a h (vacancy) 7b h ilr1 interrupt level setting register 1 w 11111111 b 7c h ilr2 interrupt level setting register 2 w 11111111 b 7d h ilr3 interrupt level setting register 3 w 11111111 b 7e h ilr4 interrupt level setting register 4 w 11111111 b 7f h itr interrupt test register access prohibited 11111111 b address register name register description read/write initial value 480 h wrarh1 wild register high-byte address register1 r/w xxxxxxxx b 481 h wrarl1 wild register low-byte address register1 r/w xxxxxxxx b 482 h wrdr1 wild register data register1 r/w xxxxxxxx b 483 h wrarh2 wild register high-byte address register2 r/w xxxxxxxx b 484 h wrarl2 wild register low-byte address register2 r/w xxxxxxxx b 485 h wrdr2 wild register data register2 r/w xxxxxxxx b 486 h wrarh3 wild register high-byte address register3 r/w xxxxxxxx b 487 h wrarl3 wild register low-byte address register3 r/w xxxxxxxx b 488 h wrdr3 wild register data register3 r/w xxxxxxxx b 489 h wrarh4 wild register high-byte address register4 r/w xxxxxxxx b 48a h wrarl4 wild register low-byte address register4 r/w xxxxxxxx b 48b h wrdr4 wild register data register4 r/w xxxxxxxx b 48c h wrarh5 wild register high-byte address register5 r/w xxxxxxxx b 48d h wrarl5 wild register low-byte address register5 r/w xxxxxxxx b 48e h wrdr5 wild register data register5 r/w xxxxxxxx b 48f h wrarh6 wild register high-byte address register6 r/w xxxxxxxx b 490 h wrarl6 wild register low-byte address register6 r/w xxxxxxxx b 491 h wrdr6 wild register data register6 r/w xxxxxxxx b
26 mb89560h series n electrical characteristics 1. absolute maximum ratings (av ss = v ss = 0.0 v) * : use av cc and v cc set at the same voltage. take care so that avr and av cc + 0.3v does not exceed v cc , such as when power is turned on. precautions: permanent device damage may occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter symbol value unit remarks min. max. power supply voltage v cc av cc v ss C 0.3 v ss + 6.0 v MB89567h, MB89567hc, mb89p568 and mb89pv560 avr v ss C 0.3 v ss + 6.0 v program voltage v pp v ss C 0.6 v ss +13.0 v only for the mb89p568 input voltage v i v ss C 0.3 v cc + 0.3 v for pins other than p30 and p31 v ss C 0.3 v ss + 6.0 v for p30 and p31 output voltage v o v ss C 0.3 v cc + 0.3 v for pins other than p30 and p31 v ss C 0.3 v ss + 6.0 v for p30 and p31 h level maximum output current i ol ? 15 ma l level average output current i olav ? 4ma average value (operating current operating rate) l level total maximum output current ? i ol ? 100 ma l level total average output current ? i olav ? 40 ma average value (operating current operating rate) h level maximum output current i oh ? C15 ma h level average output current i ohav ? C4 ma average value (operating current operating rate) h level total maximum output current ? i oh ? C50 ma h level total average output current ? i ohav ? C20 ma average value (operating current operating rate) power consumption p d ? 300 mw operating temperature t a C40 +85 c storage temperature tstg C55 +150 c
27 mb89560h series 2. recommended operating conditions (av ss = v ss = 0.0 v) * : these values depend on the operating conditions and the analog assurance range. see figure 1, figure 2, figure 3 and 5. a/d converter electrical characteristics. figure 1 operating voltage vs. main clock operating frequency parameter symbol value unit remarks min. max. power supply voltage v cc av cc 3.5* 5.5* v for MB89567h and MB89567hc 3.0 5.5 v retains the ram state in stop mode for MB89567h and MB89567hc 2.7* 5.5* v for mb89pv560 and mb89p568 1.5 5.5 v retains the ram state in stop mode for mb89pv560 and mb89p568 a/d converter reference input voltage avr 3.5 av cc v operating temperature t a C40 +85 c 2.0 4.0 5.0 3.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 operating voltage (v) 4.0 2.0 0.4 0.8 main clock operating freq. (mhz) min execution time (inst. cycle) ( m s) 2.7 3.5 12.0 11.0 12.5 0.32 5.5 : mb89p568, mb89pv560 : MB89567h, mb89p567hc operation assurance range a/d converter accuracy assurance range : vcc = avcc =3.5v~5.5v
28 mb89560h series 3. dc characteristics (av cc = v cc = 5.0v, av ss = v ss = 0.0 v, t a = C40 c to +85 c) (continued) parameter symbol pin condition value unit remarks min. typ. max. h level input voltage v ih p00 to p07, p10 to p17, p20 to p27, p30 to p37 p40 to p45 0.7 v cc v cc + 0.3 v v ihs rst , moda int10 to int17, int20 to int23, si,sck,ec1,uck, sck1,ui,si1,pwc 0.8 v cc v cc + 0.3 v v ihsmb sdl, sda v ss +1.4 v ss + 5.5 v smb input buffer selected v ihi2c 0.7 v cc v cc + 0.3 v i2c input buffer selected l level input voltage v il p00 to p07, p10 to p17, p20 to p27, p40 to p45 v ss - 0.3 0.3 v cc v v ils rst , moda int10 to int17, int20 to int23, si,sck,ec1,uck, sck1,ui,si1,pwc v ss - 0.3 0.2 v cc v v ilsmb scl, sda v ss - 0.3 v ss + 0.6 v smb input buffer selected v ili2c v ss - 0.3 0.3 v cc v i2c input buffer selected open-drain output pin application voltage v d p60 to p67 p50 to p57 p46, p47 p30, p31 v ss - 0.3 v cc + 0.3 v h level output voltage v oh p00 to p07, p10 to p17, p40 to p45 i oh = C2.0 ma 4.0 v p20 to p27 i oh = C15.0 ma l level output voltage v ol p00 to p07, p10 to p17, p30 to p31, p40 to p47, p50 to p57, p60 to p67, rst i ol = 4.0 ma 0.4v p20 to p27 i ol = 15.0 ma
29 mb89560h series (continued) (av cc = v cc = 5.0v, av ss = v ss = 0.0 v, t a = C40 c to +85 c) (continued) parameter symbol pin condition value unit remarks min. typ. max. power supply current i cc1 v cc f ch = 10.0 mhz v cc = 5.0 v t inst *3 = 0.4 m s main clock run mode 1520 ma mb89pv560 mb89p568 610 MB89567h MB89567hc i cc2 f ch = 10.0 mhz v cc = 5.0 v t inst *3 = 6.4 m s main clock run mode 58.5 ma mb89pv560 mb89p568 1.5 3 MB89567h MB89567hc i ccs1 f ch = 10.0 mhz v cc = 5.0 v t inst *3 = 0.4 m s main clock sleep mode 5 7 ma mb89pv560 mb89p568 2 4 MB89567h MB89567hc i ccs2 f ch = 10.0 mhz v cc = 5.0 v t inst *3 = 6.4 m s main clock sleep mode 1.5 3 ma mb89pv560 mb89p568 1 2 MB89567h MB89567hc i ccl f cl = 32.768 khz v cc = 5.0 subclock mode 3 7ma mb89pv560 mb89p568 2050 m a MB89567h MB89567hc i ccls f cl = 32.768 khz v cc = 5.0 v subclock sleep mode 3050 m a mb89pv560 mb89p568 1530 MB89567h MB89567hc i cct f cl = 32.768 khz v cc = 3.0 v watch mode main clock stop mode 515 m a i cch t a = +25 c subclock stop mode 310 m a i a av cc f ch = 10.0 mhz, 4 6 ma when a/d conversion is activated i ah f ch = 10.0 mhz, t a = +25 c, 1 5 m a when a/d conversion is stopped
30 mb89560h series (continued) (av cc = v cc = 5.0v, , av ss = v ss = 0.0 v, t a = C40 c to +85 c) parameter symbol pin condition value unit remarks min. typ. max. input leakage current i li p00 to p07, p10 to p17, p20 to p27, p40 to p45, p50 to p57, p60 to p67 0.0v < v i < v cc -5 + 5 m a without pull-up resister moda -10 +10 m a open-drain output leakage current i liod p30, p32 p46, p47 0.0v < v i < v ss + 5.5v +5 m a pull-up resistance r pull p00 to p07, p10 to p17, p20 to p27, p30 to p31, p40 to p45, rst v i = 0.0 v 25 50 100 k w when pull- up resistor selected except rst lcd divided resistance r lcd between v cc and v ss 300 500 750 k w com0 to com3 output impedance r vcom com0 to 3 v1 to v3 = 5.0v 2.5k w seg0 to 23 output impedance r vseg seg0 to 23 15 k w lcd controller/ driver leakage current i lcdl v0 to v3, com0 to 3 seg0 to 23 + 1 m a input capacitance c in other than av cc , av ss , v cc , and v ss f = 1 mhz 10 pf
31 mb89560h series 4. ac characteristics (1) reset timing (v cc = 5.0v, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : t hcyl is the oscillation cycle (1/f c ) to input to the x0 pin. (2) power-on reset (av ss = v ss = 0.0 v, t a = C40 c to +85 c) note: make sure that power supply rises within the selected oscillation stabilization time. for example, when the main clock is operating at 10 mhz (f ch ) and the oscillation stabilization time select option has been set to 2 18 /f ch , the oscillation stabilization delay time is 26.2 ms. therefore, the maximum value of power supply rising time is about 26.2 ms. rapid changes in power supply voltage may cause a power-on reset. if power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. parameter symbol condition value unit remarks min. max. rst l pulse width t zlzh 48 t hcyl* ns parameter symbol condition value unit remarks min. max. power supply rising time t r 0.5 50 ms power supply cut-off time t off 1 ms due to repeated operations t zlzh 0.2 v cc 0.2 v cc rst 0.2 v 0.2 v 3.5 v 0.2 v t r v cc t off
32 mb89560h series (3) clock timing (av ss = v ss = 0.0 v, t a = C40 c to +85 c) parameter symbol pin value unit remarks min. typ. max. clock frequency f ch x0, x1 1 12.5 mhz main clock f cl x0a, x1a 32.768 khz subclock clock cycle time t hcyl x0, x1 80 1000 ns main clock t lcyl x0a, x1a 30.5 m s subclock input clock pulse width p wh p wl x0 20 ns external clock p wh p wl x0a 15.2 m s external clock input clock rising/falling time t cr t cf x0 10 ns external clock 0.2 v cc 0.8 v cc x0 0.2 v cc t cr p wh t cf 0.8 v cc 0.2 v cc x0 x1 x0 x1 when a crystal or ceramic reasonator is used when an external clock is used open t hcyl p wl f ch c1 c2 f ch x0 and x1 timing and conditions main clock conditions
33 mb89560h series (4) instruction cycle parameter symbol value unit remarks instruction cycle (minimum execution time) t inst 4/f ch , 8/f ch , 16/f ch , 64/f ch m s t inst = 0.32 m s when operating at f ch = 12.5 mhz (4/f ch ) 2/f cl m s t inst = 61.036 m s when operating at f cl = 32.768 khz x0a x0a x1a x0a x1a open 0.2 v cc 0.8 v cc 0.2 v cc t cr t cf 0.8 v cc 0.2 v cc t lcyl p wlh p wll when a crystal or ceramic reasonator is used when an external clock is used f cl c1 c2 f cl x0a and x1a timing and conditions subclock conditions
34 mb89560h series (5) serial i/o timing (vcc = 5.0v, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst , see (4) instruction cycle. parameter symbol pin condition value unit remarks min. max. serial clock cycle time t scyc sck, sck1, uck internal shift clock mode 2 t inst * m s sck ? so time t slov sck, so, sck1, so1, uck, uo C200 200 ns valid si ? sck - t ivsh si, sck, si1, sck1, ui, uck 200 ns sck - ? valid si hold time t shix sck, si, sck1, si1, uck, ui 200 ns serial clock h pulse width t shsl sck, sck1, uck external shift clock mode 1 t inst * m s serial clock l pulse width t slsh 1 t inst * m s sck ? so time t slov sck, so, sck1, so1, uck, uo 0200ns valid si ? sck - t ivsh si, sck, si1, sck1, ui, uck 200 ns sck - ? valid si hold time t shix sck, si, sck1, si1, uck, ui 200 ns internal shift clock mode 0.8 v 2.4 v t scyc 2.4 v 0.2 v cc t shix 0.8 v 0.8 v t ivsh 0.8 v cc 0.2 v cc 0.8 v cc sck sck1 uck so so1 uo si si1 u1 t slov 0.2 v cc 0.8 v cc t slsh 2.4 v 0.2 v cc 0.8 v cc 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc sck sck1 uck so so1 uo si si1 ui 0.2 v cc t shsl t shix t ivsh t slov external shift clock mode
35 mb89560h series (6) peripheral input timing (vcc = 5.0v, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst, see (4) instruction cycle. parameter symbol pin condition value unit remarks min. max. peripheral input h pulse width 1 t ilih1 int10 to int17, int20 to int23, ec, pwc 2 t inst * m s peripheral input l pulse width 1 t ihil1 2 t inst * m s 0.2 v cc 0.8 v cc t ihil1 0.8 v cc int10 to 17, int20 to int23 ec, pwc 0.2 v cc t ilih1
36 mb89560h series (7) i 2 c timing (vcc = 5.0v, av ss = v ss = 0.0 v, t a = C40 c to +85 c) ? for information in t inst , see "(4) instruction cycle". ? m is defined in the iccr cs4 and cs3 (bit 4 to bit 3) ? n is defined in the iccr cs2 to cs0 (bit 2 to bit 0) parameter symbol pin condition value unit remarks min. max. start condition output t sta scl sda 1/4t inst x m x n - 20 1/4t inst x m x n + 20 ns master mode stop condition output t sto scl sda 1/4t inst x (m x n + 8) - 20 1/4t inst x (m x n + 8) + 20 ns master mode start condition detect t sta scl sda 1/4t inst x 6 + 40 ns stop condition detect t sto scl sda 1/4t inst x 6 + 40 ns re-start condition output t stasu scl sda 1/4t inst x (m x n + 8) - 20 1/4t inst x (m x n + 8) + 20 ns master mode re-start condition detect t stasu scl sda 1/4t inst x 4 + 40 ns scl output low width t low scl 1/4t inst x m x n - 20 1/4t inst x m x n + 20 ns master mode scl output high width t high scl 1/4t inst x (m x n + 8) - 20 1/4t inst x (m x n + 8) + 20 ns master mode sda output delay t do sda 1/4t inst x 4 - 20 1/4t inst x 4 + 20 ns sda output setup time after interrupt t dosu sda 1/4t inst x 4 - 20 ns scl input low pulse width t low scl 1/4t inst x 6 + 40 ns scl input high pulse width t high scl 1/4 t inst x 2 + 40 ns sda input setup time t su sda 40 ns sda hold time t ho sda 0 ns sda scl sda scl 1 ack 9 6 78 9 t do t stasu t sta t low t ho t do t su t ho t dosu t su t ho t do t do t dosu t high t low t sto data transmit (master/slave) data receive (master/slave) ack
37 mb89560h series 5. a/d converter electrical characteristics (1) for MB89567h a/d converter (avcc=3.5~5.5v, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : 1 for information on t inst , see (4) instruction cycle in 4. ac characteristics. * : 2 when a/d conversion is not in operation, and the cpu is in stop mode. * : 3 included sampling time parameter symbol pin condition value unit remarks min. typ. max. resolution 10bit 1lsb = avr/1024 total error avr=av cc 5.0 lsb non-linearity error 2.5 lsb differential linearity error 1.9 lsb zero transition voltage v ot avr - 3.5 lsb avr + 0.5 lsb avr + 4.5 lsb mv full-scale transition voltage v fst avr C 6.5 lsb avr C 1.5 lsb avr + 1.5 lsb mv interchannel disparity 4 lsb 1lsb = avr/1024 a/d mode conversion time *3 60 t inst *1 m s a/d sampling time 16 t inst *1 analog port input current i ain an0 to an7 10 m a analog input voltage v ain avss avr v reference voltage avr avss+3.5 av cc v reference voltage supply current i r a/d is activated 400 m a i rh a/d is stopped 5 m a *2
38 mb89560h series (2) for mb89p568 a/d converter (avcc=3.5~5.5v, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : 1 for information on t inst , see (4) instruction cycle in 4. ac characteristics. * : 2 when a/d conversion is not in operation, and the cpu is in stop mode. * : 3 included sampling time * : parameter symbol pin condition value unit remarks min. typ. max. resolution 10bit 1lsb = avr/1024 total error avr=av cc 3 . 0lsb non-linearity error 2.5 lsb differential linearity error 1.9 lsb zero transition voltage v ot avr - 1.5 lsb avr + 0.5 lsb avr + 2.5 lsb mv full-scale transition voltage v fst avr C 3.5 lsb avr C 1.5 lsb avr + 1.5 lsb mv interchannel disparity 4 lsb 1lsb = avr/1024 a/d mode conversion time *3 60 t inst *1 m s a/d sampling time 16 t inst *1 analog port input current i ain an0 to an7 10 m a analog input voltage v ain avss avr v reference voltage avr avss+3.5 av cc v reference voltage supply current i r a/d is activated 400 m a i rh a/d is stopped 5 m a *2
39 mb89560h series (3) precautions ? the smaller the | avrCav ss |, the greater the error would become relatively. ? the output impedance of the external circuit for the analog input must satisfy the following conditions: output impedance of the external circuit < approx. 10 k w ? if the output impedance of the external circuit is too high, an analog voltage sampling time might be insufficient (sampling time = 6 m s at 10mhz oscillation.) (4) a/d converter glossary ? resolution analog changes that are identifiable with the a/d converter. ? linearity error the deviation of the straight line connecting the zero transition point (00 0000 0000 ? 00 0000 0001) with the full-scale transition point (11 1111 1110 ? 11 1111 1111) from actual conversion characteristics ? differential linearity error the deviation of input voltage needed to change the output code by 1 lsb from the theoretical value ? total error (unit: lsb) the difference between theoretical and actual conversion values caused by the zero transition error, full-scale transition error, linearity error, quantization error, and noise (continued) analog input pin sample hold circuit c = 33 pf if the analog input impedance is higher than 10 kw, it is recommended to connect an external capacitor of approx. 0.1 mf. comparator r = 6 kw analog channel selector close for 8 instruction cycles after activating a/d conversion. . . . . analog input circuit model 0.5 lsb 1 lsb analog input av ss 1.5 lsb theoretical i/o characteristics 3ff 3fe 3fd 004 003 002 001 avr theoretical value analog input av ss v nt actual conversion value total error 3ff 3fe 3fd 004 003 002 001 avr {1 lsb n + 0.5 lsb} v fst v ot actual conversion value digital output n total error = v nt ?{1 lsb n + 0.5 lsb} 1 lsb 1 lsb = v fst ? ot 1022 digital output digital output (v)
40 mb89560h series (continued) analog input av ss linearity error 3ff 3fe 3fd 004 003 002 001 avr theoretical value analog input av ss v nt v (n + 1)t actual conversion value differential linearity error n + 1 n n ?1 n ?2 avr v nt v ot (actual measurement) actual conversion value actual conversion value digital output n differential linearity error = 1 lsb v (n + 1)t ? nt digital output digital output digital output n linearity error = v nt {1 lsb n + v ot } 1 lsb ?1 {1 lsb n + v ot } actual conversion value v fst (actual measurement) theoretical value analog input av ss zero transition error 004 003 002 001 theoretical value analog input actual conversion value full-scale transition error avr actual conversion value digital output digital output actual conversion value actual conversion value v ot (actual measurement) v fst (actual measurement) 3ff 3fe 3fd 3fc
41 mb89560h series n instructions execution instructions can be divided into the following four groups: ? transfer ? arithmetic operation ? branch ?others table 1 lists symbols used for notation of instructions. table 1 instruction symbols (continued) symbol meaning dir direct address (8 bits) off offset (8 bits) ext extended address (16 bits) #vct vector table number (3 bits) #d8 immediate data (8 bits) #d16 immediate data (16 bits) dir: b bit direct address (8:3 bits) rel branch relative address (8 bits) @ register indirect (example: @a, @ix, @ep) a accumulator a (whether its length is 8 or 16 bits is determined by the instruction in use.) ah upper 8 bits of accumulator a (8 bits) al lower 8 bits of accumulator a (8 bits) t temporary accumulator t (whether its length is 8 or 16 bits is determined by the instruction in use.) th upper 8 bits of temporary accumulator t (8 bits) tl lower 8 bits of temporary accumulator t (8 bits) ix index register ix (16 bits)
42 mb89560h series (continued) columns indicate the following: mnemonic: assembler notation of an instruction ~: number of instructions #: number of bytes operation: operation of an instruction tl, th, ah: a content change when each of the tl, th, and ah instructions is executed. symbols in the column indicate the following: ? C indicates no change. ? dh is the 8 upper bits of operation description data. ? al and ah must become the contents of al and ah immediately before the instruction is executed. ? 00 becomes 00. n, z, v, c: an instruction of which the corresponding flag will change. if + is written in this column, the relevant instruction will change its corresponding flag. op code: code of an instruction. if an instruction is more than one code, it is written according to the following rule: example: 48 to 4f ? this indicates 48, 49, ... 4f. symbol meaning ep extra pointer ep (16 bits) pc program counter pc (16 bits) sp stack pointer sp (16 bits) ps program status ps (16 bits) dr accumulator a or index register ix (16 bits) ccr condition code register ccr (8 bits) rp register bank pointer rp (5 bits) ri general-purpose register ri (8 bits, i = 0 to 7) indicates that the very is the immediate data. (whether its length is 8 or 16 bits is determined by the instruction in use.) ( ) indicates that the contents of is the target of accessing. (whether its length is 8 or 16 bits is determined by the instruction in use.) (( )) the address indicated by the contents of is the target of accessing. (whether its length is 8 or 16 bits is determined by the instruction in use.)
43 mb89560h series table 2 transfer instructions (48 instructions) notes: during byte transfer to a, t ? a is restricted to low bytes. operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (reverse arrangement of f 2 mc-8 family) mnemonic ~ # operation tl th ah n z v c op code mov dir,a mov @ix +off,a mov ext,a mov @ep,a mov ri,a mov a,#d8 mov a,dir mov a,@ix +off mov a,ext mov a,@a mov a,@ep mov a,ri mov dir,#d8 mov @ix +off,#d8 mov @ep,#d8 mov ri,#d8 movw dir,a movw @ix +off,a movw ext,a movw @ep,a movw ep,a movw a,#d16 movw a,dir movw a,@ix +off movw a,ext movw a,@a movw a,@ep movw a,ep movw ep,#d16 movw ix,a movw a,ix movw sp,a movw a,sp mov @a,t movw @a,t movw ix,#d16 movw a,ps movw ps,a movw sp,#d16 swap setb dir: b clrb dir: b xch a,t xchw a,t xchw a,ep xchw a,ix xchw a,sp movw a,pc 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 5 4 2 3 4 5 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 3 1 1 3 2 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 (dir) ? (a) ( (ix) +off ) ? (a) (ext) ? (a) ( (ep) ) ? (a) (ri) ? (a) (a) ? d8 (a) ? (dir) (a) ? ( (ix) +off) (a) ? (ext) (a) ? ( (a) ) (a) ? ( (ep) ) (a) ? (ri) (dir) ? d8 ( (ix) +off ) ? d8 ( (ep) ) ? d8 (ri) ? d8 (dir) ? (ah),(dir + 1) ? (al) ( (ix) +off) ? (ah), ( (ix) +off + 1) ? (al) (ext) ? (ah), (ext + 1) ? (al) ( (ep) ) ? (ah),( (ep) + 1) ? (al) (ep) ? (a) (a) ? d16 (ah) ? (dir), (al) ? (dir + 1) (ah) ? ( (ix) +off), (al) ? ( (ix) +off + 1) (ah) ? (ext), (al) ? (ext + 1) (ah) ? ( (a) ), (al) ? ( (a) ) + 1) (ah) ? ( (ep) ), (al) ? ( (ep) + 1) (a) ? (ep) (ep) ? d16 (ix) ? (a) (a) ? (ix) (sp) ? (a) (a) ? (sp) ( (a) ) ? (t) ( (a) ) ? (th),( (a) + 1) ? (tl) (ix) ? d16 (a) ? (ps) (ps) ? (a) (sp) ? d16 (ah) ? (al) (dir): b ? 1 (dir): b ? 0 (al) ? (tl) (a) ? (t) (a) ? (ep) (a) ? (ix) (a) ? (sp) (a) ? (pc) C C C C C al al al al al al al C C C C C C C C C al al al al al al C C C C C C C C C C C C C C C al al C C C C C C C C C C C C C C C C C C C C C C C C C ah ah ah ah ah ah C C C C C C C C C C C C C C C C ah C C C C C C C C C C C C C C C C C C C C C C C C C dh dh dh dh dh dh dh C C dh C dh C C C dh C C al C C C dh dh dh dh dh C C C C C C C C C C C C C C C C C C C C + + C C + + C C + + C C + + C C + + C C + + C C + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + C C + + C C + + C C + + C C + + C C + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C 45 46 61 47 48 to 4f 04 05 06 60 92 07 08 to 0f 85 86 87 88 to 8f d5 d6 d4 d7 e3 e4 c5 c6 c4 93 c7 f3 e7 e2 f2 e1 f1 82 83 e6 70 71 e5 10 a8 to af a0 to a7 42 43 f7 f6 f5 f0
44 mb89560h series table 3 arithmetic operation instructions (62 instructions) (continued) mnemonic ~ # operation tl th ah n z v c op code addc a,ri addc a,#d8 addc a,dir addc a,@ix +off addc a,@ep addcw a addc a subc a,ri subc a,#d8 subc a,dir subc a,@ix +off subc a,@ep subcw a subc a inc ri incw ep incw ix incw a dec ri decw ep decw ix decw a mulu a divu a andw a orw a xorw a cmp a cmpw a rorc a rolc a cmp a,#d8 cmp a,dir cmp a,@ep cmp a,@ix +off cmp a,ri daa das xor a xor a,#d8 xor a,dir xor a,@ep xor a,@ix +off xor a,ri and a and a,#d8 and a,dir 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 2 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 (a) ? (a) + (ri) + c (a) ? (a) + d8 + c (a) ? (a) + (dir) + c (a) ? (a) + ( (ix) +off) + c (a) ? (a) + ( (ep) ) + c (a) ? (a) + (t) + c (al) ? (al) + (tl) + c (a) ? (a) - (ri) - c (a) ? (a) - d8 - c (a) ? (a) - (dir) - c (a) ? (a) - ( (ix) +off) - c (a) ? (a) - ( (ep) ) - c (a) ? (t) - (a) - c (al) ? (tl) - (al) - c (ri) ? (ri) + 1 (ep) ? (ep) + 1 (ix) ? (ix) + 1 (a) ? (a) + 1 (ri) ? (ri) - 1 (ep) ? (ep) - 1 (ix) ? (ix) - 1 (a) ? (a) - 1 (a) ? (al) (tl) (a) ? (t) / (al),mod ? (t) (a) ? (a) (t) (a) ? (a) (t) (a) ? (a) " (t) (tl) - (al) (t) - (a) (a) - d8 (a) - (dir) (a) - ( (ep) ) (a) - ( (ix) +off) (a) - (ri) decimal adjust for addition decimal adjust for subtraction (a) ? (al) " (tl) (a) ? (al) " d8 (a) ? (al) " (dir) (a) ? (al) " ( (ep) ) (a) ? (al) " ( (ix) +off) (a) ? (al) " (ri) (a) ? (al) (tl) (a) ? (al) d8 (a) ? (al) (dir) C C C C C C C C C C C C C C C C C C C C C C C dl C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C 00 C C C C C C C C C C C C C C C C C C C C C C C C C C C C dh C C C C C C dh C C C C dh C C C dh dh 00 dh dh dh C C C C C C C C C C C C C C C C C C C C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + C C C C C C C C C + + C C + + + C C C C C C C C C + + C C C C C C C C C C + + r C + + r C + + r C + + + + + + + + + + C + + + C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C 28 to 2f 24 25 26 27 23 22 38 to 3f 34 35 36 37 33 32 c8 to cf c3 c2 c0 d8 to df d3 d2 d0 01 11 63 73 53 12 13 03 02 14 15 17 16 18 to 1f 84 94 52 54 55 57 56 58 to 5f 62 64 65 a c ? ? ?? a c
45 mb89560h series (continued) table 4 branch instructions (17 instructions) table 5 other instructions (9 instructions) mnemonic ~ # operation tl th ah n z v c op code and a,@ep and a,@ix +off and a,ri or a or a,#d8 or a,dir or a,@ep or a,@ix +off or a,ri cmp dir,#d8 cmp @ep,#d8 cmp @ix +off,#d8 cmp ri,#d8 incw sp decw sp 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 (a) ? (al) ( (ep) ) (a) ? (al) ( (ix) +off) (a) ? (al) (ri) (a) ? (al) (tl) (a) ? (al) d8 (a) ? (al) (dir) (a) ? (al) ( (ep) ) (a) ? (al) ( (ix) +off) (a) ? (al) (ri) (dir) C d8 ( (ep) ) C d8 ( (ix) + off) C d8 (ri) C d8 (sp) ? (sp) + 1 (sp) ? (sp) C 1 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + + + + + + + + + + + + + + + C C C C C C C C 67 66 68 to 6f 72 74 75 77 76 78 to 7f 95 97 96 98 to 9f c1 d1 mnemonic ~ # operation tl th ah n z v c op code bz/beq rel bnz/bne rel bc/blo rel bnc/bhs rel bn rel bp rel blt rel bge rel bbc dir: b,rel bbs dir: b,rel jmp @a jmp ext callv #vct call ext xchw a,pc ret reti 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 if z = 1 then pc ? pc + rel if z = 0 then pc ? pc + rel if c = 1 then pc ? pc + rel if c = 0 then pc ? pc + rel if n = 1 then pc ? pc + rel if n = 0 then pc ? pc + rel if v " n = 1 then pc ? pc + rel if v " n = 0 then pc ? pc + rei if (dir: b) = 0 then pc ? pc + rel if (dir: b) = 1 then pc ? pc + rel (pc) ? (a) (pc) ? ext vector call subroutine call (pc) ? (a),(a) ? (pc) + 1 return from subrountine return form interrupt C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C dh C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + C C C + C C C C C C C C C C C C C C C C C C C C C C C C C C restore fd fc f9 f8 fb fa ff fe b0 to b7 b8 to bf e0 21 e8 to ef 31 f4 20 30 mnemonic ~ # operation tl th ah n z v c op code pushw a popw a pushw ix popw ix nop clrc setc clri seti 4 4 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C C C C C C C C C C C C C C C C C C C dh C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C r C C C s C C C C C C C C 40 50 41 51 00 81 91 80 90
46 mb89560h series n instruction map 0123456789abcdef 0 nop swap ret reti pushw a popw a mov a,ext movw a,ps clri seti clrb dir: 0 bbc dir: 0,rel incw a decw a jmp @a movw a,pc 1 mulu a divu a jmp addr16 call addr16 pushw ix popw ix mov ext,a movw ps,a clrc setc clrb dir: 1 bbc dir: 1,rel incw sp decw sp movw sp,a movw a,sp 2 rolc a cmp a addc a subc a xch a, t xor a and a or a mov @a,t mov a,@a clrb dir: 2 bbc dir: 2,rel incw ix decw ix movw ix,a movw a,ix 3 rorc a cmpw a addcw a subcw a xchw a, t xorw a andw a orw a movw @a,t movw a,@a clrb dir: 3 bbc dir: 3,rel incw ep decw ep movw ep,a movw a,ep 4 mov a,#d8 cmp a,#d8 addc a,#d8 subc a,#d8 xor a,#d8 and a,#d8 or a,#d8 daa das clrb dir: 4 bbc dir: 4,rel movw a,ext movw ext,a movw a,#d16 xchw a,pc 5 mov a,dir cmp a,dir addc a,dir subc a,dir mov dir,a xor a,dir and a,dir or a,dir mov dir,#d8 cmp dir,#d8 clrb dir: 5 bbc dir: 5,rel movw a,dir movw dir,a movw sp,#d16 xchw a,sp 6 mov a,@ix +d cmp a,@ix +d addc a,@ix +d subc a,@ix +d mov @ix +d,a xor @a,ix +d and a,@ix +d or a,@ix +d mov @ix +d,#d8 cmp @ix +d,#d8 clrb dir: 6 bbc dir: 6,rel movw a,@ix +d movw @ix +d,a movw ix,#d16 xchw a,ix 7 mov a,@ep cmp a,@ep addc a,@ep subc a,@ep mov @ep,a xor a,@ep and a,@ep or a,@ep mov @ep,#d 8 cmp @ep,#d 8 clrb dir: 7 bbc dir: 7,rel movw a,@ep movw @ep,a movw ep,#d16 xchw a,ep 8 mov a,r0 cmp a,r0 addc a,r0 subc a,r0 mov r0,a xor a,r0 and a,r0 or a,r0 mov r0,#d8 cmp r0,#d8 setb dir: 0 bbs dir: 0,rel inc r0 dec r0 callv #0 bnc rel 9 mov a,r1 cmp a,r1 addc a,r1 subc a,r1 mov r1,a xor a,r1 and a,r1 or a,r1 mov r1,#d8 cmp r1,#d8 setb dir: 1 bbs dir: 1,rel inc r1 dec r1 callv #1 bc rel a mov a,r2 cmp a,r2 addc a,r2 subc a,r2 mov r2,a xor a,r2 and a,r2 or a,r2 mov r2,#d8 cmp r2,#d8 setb dir: 2 bbs dir: 2,rel inc r2 dec r2 callv #2 bp rel b mov a,r3 cmp a,r3 addc a,r3 subc a,r3 mov r3,a xor a,r3 and a,r3 or a,r3 mov r3,#d8 cmp r3,#d8 setb dir: 3 bbs dir: 3,rel inc r3 dec r3 callv #3 bn rel c mov a,r4 cmp a,r4 addc a,r4 subc a,r4 mov r4,a xor a,r4 and a,r4 or a,r4 mov r4,#d8 cmp r4,#d8 setb dir: 4 bbs dir: 4,rel inc r4 dec r4 callv #4 bnz rel d mov a,r5 cmp a,r5 addc a,r5 subc a,r5 mov r5,a xor a,r5 and a,r5 or a,r5 mov r5,#d8 cmp r5,#d8 setb dir: 5 bbs dir: 5,rel inc r5 dec r5 callv #5 bz rel e mov a,r6 cmp a,r6 addc a,r6 subc a,r6 mov r6,a xor a,r6 and a,r6 or a,r6 mov r6,#d8 cmp r6,#d8 setb dir: 6 bbs dir: 6,rel inc r6 dec r6 callv #6 bge rel f mov a,r7 cmp a,r7 addc a,r7 subc a,r7 mov r7,a xor a,r7 and a,r7 or a,r7 mov r7,#d8 cmp r7,#d8 setb dir: 7 bbs dir: 7,rel inc r7 dec r7 callv #7 blt rel h l
47 mb89560h series n mask option no. model MB89567h MB89567hc mb89p568 mb89pv560 specification method specify when ordering mask. setting unavailable. setting unavailable. 1 main clock oscillation stabilization delay time initial value* selection (fch = 10 mhz) ? 01: 2 12 /fch (approx. 0.41 ms) ? 10: 2 16 /fch (approx. 6.55 ms) ? 11: 2 18 /fch (approx. 26.2 ms) selectable 2 18 /fch (approx. 26.2 ms) 2 18 /f ch (approx. 26.2ms) 2 lcd driving power supply ? on-chip voltage booster ? internal voltage divider (external divider resistors can be used) internal voltage booster selectable by version number -101 internal voltage divider -102 on-chip voltage booster
48 mb89560h series n ordering information part number package remarks MB89567hpfv MB89567hcpfv mb89p568pfv-101 80-pin plastic lqfp (fpt-80p-m05) without booster resistor divider MB89567hpfv MB89567hcpfv mb89p568pfv-102 with booster MB89567hpf MB89567hcpf mb89p568pf-101 80-pin plastic qfp (fpt-80p-m06) without booster resistor divider MB89567hpf MB89567hcpf mb89p568pf-102 with booster MB89567hpfm MB89567hcpfm mb89p568pfm-101 80-pin plastic lqfp (fpt-80p-m11) without booster resistor divider MB89567hpfm MB89567hcpfm mb89p568pfm-102 with booster mb89pv560cf-101 80-pin ceramic mqfp (mqp-80c-p01) without booster resistor divider mb89pv560cf-102 with booster
49 mb89560h series n package dimensions +0.20 C0.10 +.008 C.004 +0.05 C0.02 +.002 C.001 +0.08 C0.03 +.003 C.001 lead no. (stand off) index 40 61 60 41 21 20 1 80 "a" 1.50 .059 0.127 .005 0.18 .007 (.0197.0031) 0.500.08 nom (.512) ref (.374) 13.00 9.50 12.000.10(.472.004)sq 14.000.20(.551.008)sq 0 10? details of "a" part (.004.004) 0.100.10 0.500.20(.020.008) 0.10(.004) 1994 fujitsu limited f80008s-2c-4 dimension in mm (inches) c 80-pin plastic lqfp (fpt-80p-m05) (mounting height) "a" lead no. (.031.008) 0.800.20 0.30(.012) 0.25(.010) 80 65 64 41 40 25 24 1 22.300.40(.878.016) 18.40(.724)ref m 0.16(.006) (.014.004) 0.350.10 0.80(.0315)typ (.705.016) (.551.008) 14.000.20 17.900.40 20.000.20(.787.008) 23.900.40(.941.016) index 0.150.05(.006.002) (stand off) 0.05(.002)min 3.35(.132)max (.642.016) 16.300.40 ref 12.00(.472) details of "b" part 0 10? details of "a" part 0.18(.007)max 0.58(.023)max 0.10(.004) "b" 1994 fujitsu limited f80010s-3c-2 dimension in mm (inches) c (mounting height) 80-pin plastic qfp (fpt-80p-m06)
50 mb89560h series c 1995 fujitsu limited f80016s-1c-3 deminsion in mm (inches) 0.13(.005) m 0.10(.004) 1 pin index .059 .004 +.008 0.10 +0.20 1.50 "a" details of "a" part 0 10? 0.500.20 0.100.10 (.004.004) (.020.008) (stand off) 16.000.20(.630.008)sq 14.000.10(.551.004)sq 0.65(.0256)typ 0.300.10 (.012.004) 0.127 +0.05 0.02 +.002 .001 .005 12.35 15.00 (.486) ref (.591) nom 20 21 40 1 80 61 41 60 lead no. (mounting height) 80-pin plastic lqfp (fpt-80p-m11) +0.40 C0.20 +.016 C.008 +0.40 C0.20 +.016 C.008 index typ 4.50(.177) typ 6.00(.236) index area 1.50(.059)typ 1.00(.040)typ typ 1.00(.040) typ 1.50(.059) (.0315.010) 0.800.25 1.20 .047 12.00(.472)typ (.0315.010) 0.800.25 ref 18.40(.724) (.016.004) 0.400.10 1.20 .047 (.016.004) 0.400.10 max 8.70(.343) (.006.002) 0.150.05 11.68(.460)typ 9.48(.373)typ 7.62(.300)typ 0.30(.012)typ (.050.005) 1.270.13 (.713.008) 18.120.20 typ 14.22(.560) typ 12.02(.473) typ 10.16(.400) typ 24.70(.972) (.878.013) 22.300.33 (.050.005) 1.270.13 typ 0.30(.012) index area 18.70(.736)typ (.642.013) 16.300.33 (.613.008) 15.580.20 1994 fujitsu limited m80001sc-4-2 dimension in mm ( inches ) c 80-pin ceramic mqfp (mqp-80c-p01)
51 mb89560h series memo
52 mb89560h series fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-8588, japan tel: (044) 754-3763 fax: (044) 754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. semiconductor division 1250 east arques avenue sunnyvale , ca 94088-3470, usa tel: (408) 737-5600 fax: (408) 737-5999 mon. - fri.: 7 am - 5 pm (pst) toll free: (800) 866-8608 http://www.fma.fujitsu.com/ europe fujitsu mikroelektronik gmbh am siebenstein 6-10 d-63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 http://www.fujitsu-ede.com/ asia pacific fujitsu microelectronics asia pte ltd #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 http://www.fmap.com.sg/ f9806 ? fujitsu limited printed in japan all rights reserved. circuit diagrams utilizing fujitsu products are included as a means of illustrating typical semiconductor applications. complete information sufficient for construction purposes is not necessarily given. the information contained in this document has been carefully checked and is believed to be reliable. however, fujitsu assumes no responsibility for inaccuracies. the information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by fujitsu. fujitsu reserves the right to change products or specifications without notice. no part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of fujitsu. the information contained in this document are not intended for use with equipments which require extremely high reliability such as aerospace equipments, undersea repeaters, nuclear control systems or medical equipments for life support.

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